1. Field of the Invention
This disclosure relates to a flat-type capacitor for an integrated circuit that can obtain better characteristics by preventing degradation of a capacitor dielectric layer and a method of manufacturing the same.
2. Description of the Related Art
Capacitors are essential to semiconductor memory devices, radio frequency (RF) devices, mixed signal devices, and system drivers.
While capacitors for an integrated circuit (IC) may have various shapes, a typical capacitor, which is normally called a “thin flat-type capacitor,” includes parallel thin conductive layers separated by a dielectric layer.
FIG. 1 is a cross-sectional diagram of a typical flat-type capacitor for an IC. Referring to FIG. 1, to form the flat-type capacitor, a first metal layer is deposited on a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate where IC devices and metal interconnections are formed. A predetermined portion of the first metal layer is patterned to form a lower electrode 12a and a first metal interconnection 12b. 
Afterwards, a dielectric layer 14 and a metal layer for an upper electrode are sequentially deposited on the resultant structure of the semiconductor substrate 10, and then the metal layer for an upper electrode and the dielectric layer 14 are etched until a predetermined portion of the lower electrode 12a is exposed. Here, the dielectric layer 14 is etched such that the predetermined portion of the lower electrode 12a is exposed without leaving the dielectric layer 14 as a residue. Also, the predetermined portion of the lower electrode 12a is exposed so as to electrically connect the lower electrode 12a with an upper metal interconnection to be formed at a later time. Next, an interlayer dielectric (ILD) 18 is formed on the resultant structure. The ILD 18 is etched until the lower electrode 12a, the first metal interconnection 12b, and an upper electrode 16 are exposed, thereby forming via holes (not shown).
Plugs 20 are formed by filling the via holes with a conductive material, and second metal interconnections 22a, 22b, and 22c are each formed to contact the respective plugs 20. Here, the second metal interconnection 22a transmits an electric signal to the lower electrode 12a, the second metal interconnection 22b transmits an electric signal to the upper electrode 16, and the second metal interconnection 22c transmits an electric signal to the first metal interconnection 12b. 
However, in the typical flat-type capacitor, an etching by-product may be absorbed in the sidewalls of the dielectric layer 14 while the dielectric layer 14 is being etched. As a result, electrical properties of the dielectric layer 14 may be degraded. Also, when the lower electrode 12a is exposed by etching the dielectric layer 14, the lower electrode 12a may be partially etched or residue of the etched lower electrode 12a may re-sputter onto the sidewalls of the dielectric layer 14. In FIG. 1, the arrows with dotted lines indicate the direction of the residue sputtering.
The residue of the dielectric layer 14 or the lower electrode 12a, which is attached to or re-sputtered on the sidewalls of the dielectric layer 14, may be partially removed using a subsequent cleaning process. However, it is impossible to completely remove the etching residue. Therefore, additional fabrication steps are required.
In another conventional method, as shown in FIG. 2, a dielectric layer 14 is etched at the same time as a lower electrode 12a, and only an upper electrode 16 is separately etched on the dielectric layer 14. Afterwards, an ILD 18 and the dielectric layer 14 are simultaneously etched to form via holes. This method as shown in FIG. 2 is also disclosed in FIGS. 1A through 1G of U.S. Pat. No. 6,492,223 to Kanamori, et al.
In the method of FIG. 2, because the upper electrode 16 and the dielectric layer 14 are not etched at the same time, a smaller amount of etching by-product is generated on the sidewalls of the dielectric layer 14. Also, over-etching of the dielectric layer 14 is not required, thus preventing re-sputtering of the lower electrode 12a. However, the ILD 18 and the dielectric layer 14 should be simultaneously etched to form the via holes. Accordingly, since an etch selectivity of the ILD 18 differs from that of the dielectric layer 14, the ILD 18 and the dielectric layer 14 should be etched using separate processes.
In yet another conventional method, as shown in FIG. 3, a first ILD 52 is deposited on a semiconductor substrate 10, and first metal interconnections 54 and 56 are formed in predetermined portions of the first ILD 52. The first metal interconnections 54 and 56 can be formed by a known damascene method. Here, the first metal interconnection 54 is formed to a wide line width enough to contact a lower electrode to be formed later. A second ILD 58 is deposited on the first ILD 52 including the first metal interconnections 54 and 56. Then, a predetermined portion of the second ILD 58 is etched until the first metal interconnections 54 and 56 are each exposed, thereby defining a concave capacitor region (not shown) and a via hole (not shown).
Afterwards, a conductive layer for a lower electrode and a dielectric layer 66 are sequentially deposited in the capacitor region and then polished using chemical mechanical polishing (CMP). Thus, a lower electrode 62 and the dielectric layer 66 are formed in the concave capacitor region. At the same time, a first plug 64 is formed in the via hole. A conductive layer for an upper electrode is deposited on the dielectric layer 66 and the second ILD 58 so as to fill the capacitor region and then polished using CMP. Thus, an upper electrode 68 is formed to define a concave capacitor. Next, a third ILD 72 is formed on the resultant structure of the semiconductor substrate and then etched until a pad 63 extended from the lower electrode 62, the upper electrode 68, and the first plug 64 are exposed. Thus, via holes are formed. Afterwards, second plugs 74, 76, and 78 are formed by a known method in the via holes positioned in the third ILD 72. The foregoing method as shown in FIG. 3 is also disclosed in FIG. 13 of U.S. Pat. No. 5,708,559 to Brabazon, et al.
With reference to FIG. 3, because the upper electrode is formed by using CMP, an etching byproduct is not absorbed in the sidewalls of the dielectric layer 66. Also, over-etching of the dielectric layer is not required, thus preventing re-sputtering of the lower electrode 62. Furthermore, the dielectric layer 66 and the ILD 58 or 72 may not be simultaneously etched to form via holes.
However, the pad 63 extending from the lower electrode 62, the dielectric layer 66, and the upper electrode 68 are formed using CMP. Thus, if a CMP residue remains on the surface of the dielectric layer 66, a bridge may occur between the lower electrode 62 and the upper electrode 68. Also, scratches due to physical stress may occur on the lower electrode pad 63, the dielectric layer 66, and the upper electrode 68, or chemical defects like erosion can be caused by slurry. As a result, poor contact may occur between the lower electrode pad 63 and the second plug 74 and between the upper electrode 68 and the second plug 76. Further, scratches due to CMP occur in a portion of the dielectric layer 66, which is used as a substantial dielectric layer, thus degrading characteristics of the dielectric layer 66.
Because of stress focused on both sides of the concave capacitor in the region X of FIG. 3, when voltage is applied to the lower electrode 62 and the upper electrode 66, breakdown occurs in region X of the dielectric layer 66. Thus, electrical properties of the capacitor are degraded. This phenomenon results from not only the concave structure of the capacitor but also from poor deposition of the dielectric layer 66 in region X. Consequently, the capacitor of FIG. 3 cannot completely solve the problems of poor contact and a degraded dielectric layer.
Embodiments of the invention address these and other disadvantages of the prior art.